1. Field
Exemplary embodiments of the present invention relate to a semiconductor memory device, and more particularly, to a burst order control circuit for controlling a burst order in a semiconductor memory device.
2. Description of the Related Art
A semiconductor memory device determines a burst order (i.e., a data output order) in response to a start address SA and an interleave mode signal, and a control circuit for determining the burst order is called a burst order control circuit.
FIG. 1 is a block diagram of a conventional burst order control circuit 110.
Referring to FIG. 1, data transmitted through a plurality of global lines GL<0:3> are outputted through the burst order control circuit 110 to an interface pad DQ.
An operation of the burst order control circuit 110 will be described below with reference to FIG. 1.
Data transmitted in parallel through the global lines GL<0:3> are sorted in series through the burst order control circuit 110 and are outputted through the interface pad DQ. Here, the data are sorted and outputted in the order determined by a start address SA<0:1> and an interleave mode signal INT.
The start address SA<0:1> is used to designate the data to be outputted first. For example, when the data are transmitted through four global lines, the start address may be a 2-bit digital signal. Hereinafter, the value of the start address SA<0:1> is referred to as (SA<1>, SA<0>).
If the value of the start address SA<0:1> is (0, 0), the data of the first global line GL<0> (hereinafter referred to as the first data) is outputted first. If the value of the start address SA<0:1> is (0, 1), the data of the second global line GL<1> (hereinafter referred to as the second data) is outputted first. If the value of the start address SA<0:1> is (1, 0), the data of the third global line GL<2> (hereinafter referred to as the third data) is outputted first. If the value of the start address SA<0:1> is (1, 1), the data of the fourth global line GL<3> (hereinafter referred to as the fourth data) is outputted first.
The interleave mode signal INT is used to control the burst order control circuit 110 to operate in a sequential mode or in an interleave mode. The interleave mode signal INT is activated in the interleave mode and is deactivated in the sequential mode.
When the interleave mode signal INT is deactivated (i.e., the sequential mode), if the data to be outputted first is determined by the start address SA<0:1>, the data are outputted in the following order. For example, if the value of the start address SA<0:1> is (0, 0), the first data is determined to be outputted first and the data are outputted in the order of the first data, the second data, the third data, and the fourth data. If the value of the start address SA<0:1> is (1, 0), the third data is determined to be outputted first and the data are outputted in the order of the third data, the fourth data, the first data, and the second data. The case when the interleave mode signal INT is activated will be described below with reference to FIG. 2.
FIG. 2 is a diagram illustrating the data output order based on the value of the start address SA<0:1> and whether an operation mode is an interleave mode.
Referring to FIG. 2, the first data, the second data, the third data, and the fourth data are denoted by ‘D0’, ‘D1’, ‘D2’, and ‘D3’ respectively.
In the sequential mode, if the value of the start address SA<0:1> is (0, 0), the data are outputted in the order of ‘D0’, ‘D1’, ‘D2’, and ‘D3’. If the value of the start address SA<0:1> is (0, 1), the data are outputted in the order of ‘D1’, ‘D2’, ‘D3’, and ‘D0’. If the value of the start address SA<0:1> is (1, 0), the data are outputted in the order of ‘D2’, ‘D3’, ‘D0’, and ‘D1’. If the value of the start address SA<0:1> is (1, 1), the data are outputted in the order of ‘D3’, ‘D0’, ‘D1’, and ‘D2’.
In the interleave mode, if the value of the start address SA<0:1> is (0, 0), the data are outputted in the order of ‘D0’, ‘D1’, ‘D2’, and ‘D3’. If the value of the start address SA<0:1> is (0, 1), the data are outputted in the order of ‘D1’, ‘D0’, ‘D3’, and ‘D2’. If the value of the start address SA<0:1> is (1, 0), the data are outputted in the order of ‘D2’, ‘D3’, ‘D0’, and ‘D1’. If the value of the start address SA<0:1> is (1, 1), the data are outputted in the order of ‘D3’, ‘D2’, ‘D1’, and ‘D0’.
That is, in the process of transmitting the data of the global lines GL<0:3> to the interface pad DQ, the data output order is determined by changing the data transfer path in response to a signal generated using the start address SA<0:1> and the interleave mode signal INV. Here, the data is to be outputted through the interface pad DQ after the time corresponding to a read latency passes from the application of a read command. Thus, a system timing margin and a high-speed operation may be obtained by generating the signal for changing the data transfer path at proper timing.